1. Field of the Invention
Embodiments of the present invention relate to the field of circuit design. More specifically, embodiments of the present invention relates to a cascaded PLL arrangement.
2. Background Information
Over the years, ongoing advancements in the field of microprocessor design and fabrication have facilitated the continued increase in microprocessor clock frequencies. High frequency microprocessor core clocks are typically synthesized from existing, lower frequency external reference clocks such as a bus clock. In the past, it was fairly simple to achieve a desired core frequency using PLLs as microprocessor core-to-bus frequency ratios were relatively low. Nowadays however, in order to generate the multi-Gigahertz microprocessor core frequencies that are typical, a large PLL synthesis factor is required. Unfortunately, as PLL synthesis factors increase, the circuit area required to implement the PLLs also increases.
In the past, microprocessor core clock signals and microprocessor I/O clock signals have been generated by two PLLs disposed in a parallel arrangement with respect to one another. FIG. 1, for example, illustrates a prior art dual-PLL arrangement where the PLLs are arranged in a parallel configuration. As shown, the external reference clock, xclk, is routed to both I/O PLL 104 and Core PLL 114 to generate Data clock 109 and Core clock 119 respectively. In order to generate a Core clock signal having a frequency that is N times greater than the frequency of xclk, the damping factor (which is a measure of PLL stability) of Core PLL 114 is reduced by a factor equivalent to the square root of N. One problem with this arrangement, however, is that a lower damping factor can also cause jitter amplification in certain phase-modulation frequencies. Additionally, any phase noise associated with xclk will be propagated through to Core clock 119 with only one level of filtering. Moreover, since the bandwidth of Core PLL 114 is very high, the effectiveness of the phase noise filtering is reduced.
Another problem associated with the parallel PLL configuration illustrated in FIG. 1 involves the synchronous transfers between timing domains. Because the parallel PLLs do not track each other very closely, a timing margin is often required to facilitate synchronous data transfer from one timing domain to another in a deterministic manner. Unfortunately, however, such timing margins typically shrink as microprocessor core operating frequencies increase potentially resulting in clock instability.